1. Field of the Invention
The present invention relates to a data rate converter for changing the data rate of a digital signal to enable data transfer between circuits or systems having different data rate requirements.
2. Description of the Related Art
FIG. 12 shows a structure of a conventional data rate converter.
The shown data rate converter receives input data SID inputted in series from a data write-side circuit per frame synchronously with an input clock signal CKA having a stream of clock pulses, and outputs data of given first part of each frame of the input data SID in series synchronously with an output clock signal CKB having a stream of clock pulses as output data SOD to a data read-side circuit.
The data rate converter includes a 2-port random access memory (RAM) 1 which temporarily stores data for data rate conversion. The RAM 1 has a storage area of 32 (words).times.8 (bits). The RAM 1 is provided with a data input terminal DI for writing data per word (8 bits), a write address terminal AI, a write control terminal WE, a data output terminal DO for reading stored data per word, and a read address terminal AO.
The input data SID and the input clock signal CKA are inputted into a serial/parallel (S/P) conversion circuit 2. The S/P conversion circuit 2 converts the input data SID inputted in series synchronously with the input clock signal CKA into parallel data per 8 bits and holds it by a latch signal SPL for an output as write data WDT. An output side of the S/P conversion circuit 2 is connected to the data input terminal DI of the RAM 1.
A parallel/serial (P/S) conversion circuit 3 is connected to the data output terminal DO of the RAM 1 for converting read data RDT outputted from the RAM 1 in parallel, into serial data synchronously with the output clock signal CKB. Specifically, the P/S conversion circuit 3 receives 8-bit read data RDT outputted from the data output terminal DO of the RAM 1, at the timing of a latch signal PSL in parallel, and shifts the received data per bit synchronously with the output clock signal CKB for a serial output as output data SOD.
The input clock signal CKA is also fed to a S/P control circuit 4, a write address generating circuit 5 and a write control circuit 6. The S/P control circuit 4 produces a latch signal SPL in the form of a pulse per 8 clock pulses of the input clock signal CKA for feeding to the S/P conversion circuit 2. The write address generating circuit 5 reduces the number of clock pulses of the input clock signal CKA by 1/8 and counts them to sequentially produce write addresses WAD from address 0 (zero) based on the count values. An output side of the write address generating circuit 5 is connected to the write address terminal AI. The write control circuit 6 produces a write enable signal WEN in the form of a pulse per 8 clock pulses of the input clock signal CKA and outputs it to the RAM 1. Further, the write control circuit 6 outputs a ready signal RDY in the form of a pulse to the read side of the data rate converter at every timing when data writing is completed into address 0 (zero) of the RAM 1, and stops outputting a subsequent write enable signal WEN when data writing into address 31 of the RAM 1 is finished. The ready signal RDY has a given pulse width, for example, similar to that of each clock pulse of the output clock signal CKB, and is used for allowing the read side of the data rate converter to start reading data from the RAM 1.
The read side of the data rate converter comprises, in addition to the P/S conversion circuit 3, a read control circuit 7, a read address generating circuit 8 and a P/S control circuit 9. The output clock signal CKB is commonly fed to these circuits.
The read control circuit 7 comprises a D-type flip-flop having a data terminal to which the ready signal RDY is fed, a clock terminal to which the output clock signal CKB is fed, and an output terminal from which a trigger signal TRG in the form of a pulse having a given pulse width is outputted. The trigger signal TRG is given to the read address generating circuit 8 and the P/S control circuit 9. The read address generating circuit 8 starts its operation in response to the trigger signal TRG. The read address generating circuit 8 reduces the number of clock pulses of the output clock signal CKB by 1/8 and counts them to sequentially produce read addresses RAD from address 0 based on the count values. The P/S control circuit 9 starts its operation in response to the trigger signal TRG and produces a latch signal PSL in the form of a pulse per 8 clock pulses of the output clock signal CKB for feeding to the P/S conversion circuit 3.
In the foregoing data rate converter, when input data SID is received per frame synchronously with the input clock signal CKA, the input data SID is converted into parallel write data WDT per 8 bits in the S/P conversion circuit 2 and given to the data input terminal DI of the RAM 1. The write address generating circuit 5 reduces the number of clock pulses of the input clock signal CKA by 1/8 to produce write addresses WAD which are fed to the write address terminal AI in turn. The write control circuit 6 produces a write enable signal WEN per 8 clock pulses of the input clock signal CKA and feeds it to the write control terminal WE of the RAM 1. Accordingly, the input. data SID is stored into the RAM 1 from address 0 to address 31 per word (8 bits) in turn.
After the first word of the input data SID is stored into address 0 of the RAM 1, the write control circuit 6 outputs a ready signal RDY to the read control circuit 7. In response, the read control circuit 7 produces a trigger signal TRG synchronously with the output clock signal CKB and feeds it to the read address generating circuit 8 and the P/S control circuit 9. In response, the read address generating circuit 8 sequentially produces read addresses RAD increasing from address 0 and feeds them to the read address terminal AO in turn. Then, data stored in corresponding storage areas of the RAM 1 are outputted to the data output terminal DO in turn as read data RDT. The read data RDT are read into the P/S conversion circuit 3 in turn by latch signals PSL outputted from the P/S control circuit 9. The P/S conversion circuit 3 converts the read data RDT into serial data synchronously with the output clock signal CKB, and outputs the serial data as output data SOD.
Now, it is assumed that each frame of the input data SID is composed of 512 bits, the input clock signal CKA has a frequency of 4 MHz, and the output clock signal CKB has a frequency of 1.5 MHz. In this case, a ready signal RDY is outputted from the write control circuit 6 when first part 193 bits of a frame of the input data SID are read from the RAM 1 and outputted as output data SOD. Thus, the read address RAD returns to address 0 so that first part 193 bits of the next frame of the input data SID are read and outputted as output data SOD.
However, the foregoing conventional data rate converter has the following problems (1) and (2).
(1) Since the input clock signal CKA and the output clock signal CKB are asynchronous with each other, if the output clock signal CKB rises while the ready signal RDY outputted from the write control circuit 6 is rising (leading edge) or decaying (trailing edge), there is a possibility that the trigger signal TRG is not produced. As a result, the correct timing for reading data from the RAM 1 may not be attained to cause an error in the output data SOD.
(2) If the input clock signal CKA or the output clock signal CKB is omitted due to an influence of noise or the like, the write side timing and the read side timing may deviate from each other to cause an error in the output data SOD.